Instruction Format: A computer will usually have a variety of instruction code formats. It is the function of the control unit within the CPU to interpret each instruction code and provide the necessary control functions needed to process the instruction.

Each instruction for the CPU is specified by giving.

  • A code for the instruction (opcode).
  • Address of the operands.

Although other things (like addressing mode) are also specified but in most general form the instruction is specified in the format given in the figure below

4 bits                                                              6 bits                                                  6 bits

Opcode Operand Reference Operand Reference

Zero-Address Instruction Format: The name “zero-address” is given to this type of computer because of the absence of an address field in the computational instructions. A stack-organized computer does not use an address field for the instructions ADD and MUL. The PUSH and POP instruction, however, need an address field to specify the operand that communication with the stack.

One-Address Instruction Format: One-address instructions use an implied accumulator (AC) register for all data manipulation. For multiplication and division there is a need for a second register.

Two-Address Instruction Format: For two address instruction, each address field can again specify either a possible register or a memory address. Two-address instructions are the most common in commercial computers. Examples of such instructions are MOV, ADD, CMP and BIS.

Three Address Instruction: Computer with three-address instruction formats can use each address field to specify either a processor register or memory operand. The advantage of the three-address format is that it results in short programs when evaluating arithmetic expression. The disadvantage is that the binary-coded instruction formats in the computer are restricted to either three register address fields or two register address fields and one memory address field.

Fetch-decode-Execute cycle: Now that you know the basic architecture let us see how the CPU enacts the instructions, specified in a program.

When we want to execute a sequence of instructions those instructions/data are first of all loaded into the main memory of the computer by using some I/O device. Once these instructions have been loaded into main memory, the address of the first instruction is copied into the program counter and the control is given to the CPU. The CPU performs the following steps:

Fetch Instruction: The CPU reads the value of PC and the instruction pointed to by PC into the instruction register.

This fetching of instruction involves the following steps:

  • Copy the contents of PC into the MAR and request a memory read.
  • Copy the data read from the memory into MBR and instruction then in the IR. Increment PC so that it points to the next instruction.

Decode Instruction: Once the fetching of instruction is complete the CU decodes the instruction by analyzing the opcode of the instruction. It also reads the values of operands specified in the instruction. Decoding means activating the appropriate circuit to execute the instruction.

Execute Instruction: After decoding the instruction the processor executes the instruction by using the activated circuit. Then the results of the execution are written back to registers and memory.

The CPU repeatedly does these steps. These steps are known as Fetch-Decode-ExecuteCycle.

Fetch_Decode_Execute

Figure 5.11Fetch Decode Execute